XD=/usr/local/xil/Xilinx/bin/nt
SRCDIR=src
VL=clk_div.v clk_div100.v count.v
TOP=count
PRJ=$(TOP).prj
SYNT_FILE=synt_$(TOP)
UCF=$(SRCDIR)/$(TOP).ucf
SYNT=run -ifn $(PRJ) -ifmt mixed -p xc2s50-6-tq144 -ofmt NGC -ofn $(TOP) -top $(TOP)
export XIL_NGDBUILD_OLDFLOW=1


all: synt

bit: ngd map par trce bitgen

synt:
	winex3 $(XD)/xst -ifn $(SYNT_FILE) -ofn $(TOP).syr


ngd:
	winex3 $(XD)/ngdbuild -intstyle ise -uc $(UCF) -p xc2s50-tq144-6 $(TOP).ngc $(TOP).ngd


map:
	winex3 $(XD)/map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o $(TOP)_map.ncd $(TOP).ngd $(TOP).pcf


par:
	winex3 $(XD)/par -w -intstyle ise -ol std -t 1 $(TOP)_map.ncd $(TOP).ncd $(TOP).pcf


trce:
	winex3 $(XD)/trce -intstyle ise -e 3 -l 3 -xml $(TOP) $(TOP).ncd -o $(TOP).twr $(TOP).pcf


bitgen:
	winex3 $(XD)/bitgen -intstyle ise $(TOP).ncd


prep:
	> $(PRJ)
	for d in $(VL); do \
		echo "verilog work ${SRCDIR}/$${d} ">> $(PRJ);\
	done
	echo "$(SYNT)" > $(SYNT_FILE)

clean:
	rm $(SYNT_FILE)
	rm $(PRJ)